The present invention relates to a semiconductor device, and more particularly, to a semiconductor device with a channel having a FIN structure and a method for manufacturing the same.
Recently, as the design rule of a semiconductor device rapidly decreases with an increase in the integration level of the semiconductor device, it becomes more difficult to achieve the stable operation of a transistor within the semiconductor device. In particular, as the size of a transistor also decreases with a decrease in the design rule of the semiconductor device to the scale of 50 nm or less, a cell threshold voltage (Vt) and a refresh characteristic margin reach limits. Thus, various researches are being conducted to provide techniques for achieving a larger effective channel length without increasing the design rule. For example, a larger effective channel length is achieved by increasing a channel length for a limited gate linewidth. To this end, an attempt is being made to increase a channel length by means of a FIN-type transistor (FinFET) that uses a transistor including a recess channel and a FIN-type active region. However, in comparison with the pre-existing Double Data Rate (DDR) Dynamic Random Access Memory (DRAM) product, the currently-commercialized high-speed DDR2 DRAM product rapidly decreases a data retention time by setting test conditions at a high temperature. Also, a decrease in the width-direction size of an active region causes degradation in the driving current characteristic of a cell transistor. Degradation in the driving current characteristic of a cell transistor causes a Write Recovery Time (tWR) defect. Achieving a stable cell driving current involves reducing the resistance of a landing plug and a cell junction and further expanding a current path. However, as the width-direction size of an active region decreases, the current path is difficult to expand. Thus, a FIN-type transistor (FinFET) is used to achieve the expanded current path. The FinFET is formed in such a way that a device isolation layer is removed below a recess gate. However, when the subsequent process is performed after removing the device isolation layer below the recess gate, a short is generated between a landing plug and a conductive layer filling a trench formed in the device isolation layer, thus making it difficult to control a self-aligned contact (SAC) defect. An attempt has been made to perform a mask process on the device isolation layer in order to solve the above problem, but it is difficult to apply due to a limitation on patterning. There is therefore a need in the art for techniques to control the self-aligned contact (SAC) defect, which may be generated due to the short between the landing plug and the conductive layer, while achieving the margin of the cell threshold voltage, by simultaneously using the advantages of the FinFET structure and the transistor structure including the recess channel.